1. Field of the Invention
The present invention generally relates to a PLL (Phase-Locked Loop) circuit and, in particular, to a PLL circuit which can be used in a digital circuit such an a clock recovery circuit of a digital communication device.
2. Description of the Related Art
There have been proposed digital PLL circuits which are designed to reduce the phase jitter and pull-in time. For example, a digital PLL circuit disclosed in Japanese Patent Unexamined Publication No. 62-242420 is provided with a frequency divider which is capable of changing the value of divisor depending on the comparison result of a phase comparator so as to suppress variations in phase.
Another digital PLL circuit disclose in Japanese Patent Unexamined Publication No. 1-136417 is provided with an up/down counter and a time-axis adjustment controller. The up/down counter increments or decrements depending on the comparison result of a phase comparator. The time-axis adjustment controller removes or inserts a pulse from or into an oscillation pulse signal depending on a count value of the up/down counter. However, when the PLL circuit is operating in a synchronous steady state, the up/down counter stops counting, which causes the time-axis adjustment controller to stop pulse phase adjustment. Stopping the pulse phase adjustment results in reduced jitter in the synchronous steady state.
Further another digital PLL circuit disclosed in Japanese Patent Unexamined Publication No. 63-121316 is provided with a loop filter comprising an 8-bit A/D converter, a processor running a tracking program and a 16-bit D/A converter. More specifically, the processor according to the tracking program controls the center frequency of a voltage controlled oscillator (VCO) so as to reduce a phase error to zero in the synchronous steady state.